| 摘要 |
A data processing apparatus comprises processing circuitry including several state retention cells for holding a current state of the processing circuitry, at least some of the state retention cells being arranged in series. In response to a hibernate signal, the processing apparatus switches from an operational mode to a low power or sleep mode in which the processing circuitry is powered down. Prior to powering down the processing circuitry its current state is output from the state retention cells and encrypted, and the encrypted state is then stored (fig. 3a). Upon detection of a wake signal, the processing apparatus switches from the low power mode to the operational mode and the stored encrypted state data is decrypted and used to restore the state of the processing circuitry (fig. 3b). The state retention cells may take the form of one or more scan chains and provide an output in the form of one or more serial data streams. This is a convenient form for subsequent encryption by hardware logic. A hash or checksum of the state may also be calculated and stored for protecting the integrity of the data. |
