发明名称 Nonvolatile memory device with test mechanism
摘要 A nonvolatile semiconductor memory device includes a memory cell having a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a gate node coupled to a word selecting line and a source/drain node coupled to a bit line, and the MIS transistor becoming conductive in response to a first state of the word selecting line and becoming nonconductive in response to a second state of the word selecting line, and a test circuit coupled to the bit line to sense a current running through the MIS transistor, the test circuit configured to indicate error in response to either a detection of presence of the current when the word selecting line is in the second state or a detection of absence of the current when the word selecting line is in the first state.
申请公布号 US7414903(B2) 申请公布日期 2008.08.19
申请号 US20060413987 申请日期 2006.04.28
申请人 NSCORE INC. 发明人 NODA KENJI
分类号 G11C29/00 主分类号 G11C29/00
代理机构 代理人
主权项
地址