发明名称 |
Methods for forming area-efficient scan chains in integrated circuits, and integrated circuits embodying the same |
摘要 |
A method of forming a scan chain for testing an integrated circuit includes examining an interconnection of register elements in an integrated circuit design. A register element segment is identified which includes a source register element having an output and a destination register element having an input directly coupled to the output of the source register element. The segment is selectively coupled to another scan register element to form a portion of scan chain.
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申请公布号 |
US2008195991(A1) |
申请公布日期 |
2008.08.14 |
申请号 |
US20080082180 |
申请日期 |
2008.04.09 |
申请人 |
DUEWER BRUCE ELLOT;PUTMAN RICHARD DEAN |
发明人 |
DUEWER BRUCE ELLOT;PUTMAN RICHARD DEAN |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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