| 摘要 |
A frequency divider providing an odd integer division factor comprising a binary counter ( 10 ) providing an even integer division factor, which is the first even number smaller than the odd division factor, the binary counter having a clock input for receiving a periodical clock signal (Ck) having a frequency. The circuit further comprises an end of count circuit ( 20 ) coupled to the binary counter and generating an End Of Count signal (EOC) for a clock (Ck) period after every even integer number periods of the clock signal (Ck), the end of count signal (EOC) being inputted to an input (IN) of the counter ( 10 ). The circuit further includes an output generator ( 30 ) coupled to the binary counter and to the clock signal (Ck), the output generator ( 30 ) generating an output signal (OUT) having a frequency which is substantially equal with the frequency of the frequency signal (Ck) divided by the odd division factor
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