发明名称 Content processing apparatus
摘要 A content processing apparatus includes a clock circuit. The clock circuit counts time with reference to a first start-up time. A flash memory holds a storage period. A recording time based on a time of the clock circuit is embedded in a JPEG file to be recorded in a hard disk. When accepting an instruction to reproduce the JPEG file, a CPU calculates a boundary time based on a current time of the clock circuit and the storage period. Then, if the recording time of the JPEG file is earlier than the boundary time, the CPU disables a reproduction process of the JPEG file by a JPEG codec.
申请公布号 US7409072(B2) 申请公布日期 2008.08.05
申请号 US20040957732 申请日期 2004.10.05
申请人 SANYO ELECTRIC CO., LTD. 发明人 MIZUTANI ARITAKA;FUJIYAMA MICHIHIRO;HASHIMOTO SEIJI
分类号 G06F12/14;G06K9/00;H04N5/76;H04N5/765;H04N5/77;H04N5/775;H04N5/781;H04N5/783;H04N7/18;H04N9/804 主分类号 G06F12/14
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