SEMICONDUCTOR MEMORY DEVICE WITH FAIL BIT LATCH

摘要

A semiconductor memory device with a fail bit latch is provided to enable a parallel bit tester to perform testing without a fail bit memory for the semiconductor memory device. According to a semiconductor memory device comprising a memory cell array, a comparison circuit(100) compares data read after being written for parallel bit testing and then outputs comparison result data. A storing and output part(200) latches the comparison result data outputted from the comparison circuit as pass/fail data and then outputs the latched comparison result data through a plurality of output stages simultaneously when an enable signal is enabled, and outputs parallel bit test comparison data applied independently through the plurality of output stages simultaneously when the enable signal is disabled. The storing and output part comprises a latch circuit.