发明名称 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SETTING A NEGATIVE THRESHOLD VOLTAGE
摘要 In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potentials of the word lines and bit lines. The control circuit, when reading data from the memory cell connected to a first one of the bit lines, supplies a first voltage to a second bit line provided next to the first bit line and to a source line of the memory cell array.
申请公布号 US2008181019(A1) 申请公布日期 2008.07.31
申请号 US20080055074 申请日期 2008.03.25
申请人 SHIBATA NOBORU 发明人 SHIBATA NOBORU
分类号 G11C16/06 主分类号 G11C16/06
代理机构 代理人
主权项
地址