| 摘要 |
The present invention provides a multilayered bus system capable of performing transition to a power-saving mode reliably and rapidly. When a mode designation signal for designating the power-saving mode is outputted from a clock controller in response to mode setting information outputted from a CPU, respective arbiters respectively output response signals for prohibiting access to bus slaves to their corresponding bus masters. When the power-saving mode is designated by the mode designation signal, the response signal for prohibiting access is outputted from the arbiter, and an end signal indicating that the respective bus slaves do not perform data transfers for a predetermined period of time is outputted from a monitor, a control signal for stopping the supply of a system clock is outputted from the clock controller to a clock generator.
|
