发明名称 DEAD TIME CONTROL CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a dead time control circuit capable of highly accurately setting a dead time in a wide range by changing step intervals in accordance with the dead time with an IC chip of a small circuit scale without externally adding a delay element when setting the dead time in a wide range at a plurality of steps. <P>SOLUTION: A dead time control circuit 10 delays activation pulse edges of two pulse signals, adds the dead time between their non-activation pulse edges and activation pulse edges, and outputting them in parallel. The circuit 10 is provided with: delay circuit parts 101a and 101b for selecting any of a delay time at the plurality of steps with step intervals corresponding to the dead time on the basis of a control signal (DA) to delay both pulse edges of the input pulse signals; and a signal generation part (logical circuit parts 102a and 102b) for generating a signal whose activation pulse edge is delayed by performing logical processing to the input pulse signal and the pulse signal delayed by the delay circuit part. <P>COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008172323(A) 申请公布日期 2008.07.24
申请号 JP20070001372 申请日期 2007.01.09
申请人 NEC ELECTRONICS CORP 发明人 YOSHIDA MITSURU;YANAGAWA HIROSHI
分类号 H03K5/04;H02M7/537;H03K5/13;H03K5/131;H03K17/16;H03K17/687;H03K19/0175 主分类号 H03K5/04
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