发明名称 Low voltage diode with reduced parasitic resistance and method for fabricating
摘要 A method of making a diode begins by depositing an Al<SUB>x</SUB>Ga<SUB>1-x</SUB>N nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n- GaN layer, an Al<SUB>x</SUB>Ga<SUB>1-x</SUB>N barrier layer, and an SiO<SUB>2 </SUB>dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au-Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n-, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal,; and an ohmic contact is deposited on the n+ layer.
申请公布号 US2008173882(A1) 申请公布日期 2008.07.24
申请号 US20070655696 申请日期 2007.01.19
申请人 CREE, INC. 发明人 PARIKH PRIMIT;HEIKMAN STEN
分类号 H01L33/00;H01L21/00 主分类号 H01L33/00
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