| 摘要 |
PROBLEM TO BE SOLVED: To provide a boundary test architecture usable for carrying out a boundary test when an integrated circuit is under an operation mode, in the integrated circuit. SOLUTION: This test architecture used in the integrated circuit of the present invention is provided with an application logic circuit 20 of the integrated circuit having an input terminal for carrying an input data and an output terminal for carrying an output data, to execute a desired function, a serial scan route formed of a resister of the integrated circuit, and including at least one comparison data register 98 for holding comparison data loaded continuously from the scan route, and a comparison logic (COMPOUT) for generating a comparison signal (CTERM) in response to comparison of the comparison data in the comparison data register with the data in the application logic circuit, and connected to the application logic circuit and the comparison data register. COPYRIGHT: (C)2008,JPO&INPIT |
