发明名称 |
ESTIMATING STATIC POWER CONSUMPTION OF INTEGRATED CIRCUITS USING LOGIC GATE TEMPLATES |
摘要 |
A method, system and computer program product for estimating a static power consumption of an integrated circuit are disclosed. The static power consumption of a cell of the integrated circuit is characterized based on contributions of an input node(s) and an output node(s) of the cell. A contribution considers a leakage weight and a leakage probability of a node. A logic template of the cell may be created to better represent a contribution of an internal node to the static power consumption of the cell.
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申请公布号 |
US2008177487(A1) |
申请公布日期 |
2008.07.24 |
申请号 |
US20070626020 |
申请日期 |
2007.01.23 |
申请人 |
LICHTENAU CEDRIC;GARCIA-ORTIZ ALBERTO;ROHRER NORMAN J |
发明人 |
LICHTENAU CEDRIC;GARCIA-ORTIZ ALBERTO;ROHRER NORMAN J. |
分类号 |
G01R21/00 |
主分类号 |
G01R21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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