发明名称 |
Method and apparatus for controlling congestion during integrated circuit design resynthesis |
摘要 |
The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the design field. The congestion values are stored in machine-readable memory and are updated in response to wire changes within the design field.
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申请公布号 |
US7401313(B2) |
申请公布日期 |
2008.07.15 |
申请号 |
US20050258738 |
申请日期 |
2005.10.26 |
申请人 |
LSI CORPORATION |
发明人 |
GALATENKO ALEXEI V.;GASANOV ELYAR E.;LYALIN ILIYA V. |
分类号 |
G06F17/50;G06F7/00 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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