| 摘要 |
The enable timing for sense amplifiers in a memory-containing integrated circuit 2 is set in dependence on the response time of a test sense amplifier circuit. This allows the optimum sense amplifier performance to be attained for any PVT (process, voltage and temperature) conditions while reducing wasteful operation margins. The testing circuit overhead is low. The test may comprise pass/fail or statistical assessment of the test sense amplifier performance for differing applied enable timings. The testing may be conducted by an internal or external test controller 18,20 and the setting may take into account available redundancy. The testing may be performed during manufacturing test or may be performed repeatedly during IC operation or when the IC conditions change. The test sense amplifier circuit may comprise two amplifiers subject respectively to fast and slow enable pulses (figure 5). Operating voltage or clock frequency may be adapted instead of signal timing. These parameters may be stored in non-volatile memory 12,14. |
