发明名称 |
Atomic operation involving processors with different memory transfer operation sizes |
摘要 |
Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that operate on different sized register lines. A main memory address containing a primitive is divided into a parity byte and two or more portions, wherein the parity byte includes at least one bit. A value of the parity byte determines which of the two or more portions is a valid portion and which of them is an invalid portion. The primitive is of a memory size that is larger than a maximum size for atomic operation with the PPE and less than or equal to a maximum size for atomic operation with the SPE. Read with reservation and conditional write instructions are used by both the PPE and SPE to access or update a value of the atomic.
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申请公布号 |
US7398368(B2) |
申请公布日期 |
2008.07.08 |
申请号 |
US20050291306 |
申请日期 |
2005.12.01 |
申请人 |
SONY COMPUTER ENTERTAINMENT INC. |
发明人 |
MARR JAMES E.;BATES JOHN P.;VASS ATTILA;IWAMOTO TATSUYA |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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