| 摘要 |
A semiconductor memory device with a control signal tree structure of a block address coding unit is provided to reduce data control signal skew and control signal loading by reducing the number of block code signal groups. An input/output sense amplifier part(8) is located among adjacent memory banks and is shared for data access of the memory banks. Global input/output multiplexers(10,10a) are arranged symmetrically to the input/output sense amplifier part and are connected to the memory banks correspondingly. Global input/output drivers(12,12a) are located between the global input/output multiplexers and the memory banks, and perform data input/output driving for the memory banks. A column block predecoder(4) and a data control signal generator(6a-6d) are arranged in the region where the input/output sense amplifier part is located, and control signal lines are arranged to form a control signal tree structure in a block address coding unit.
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