发明名称 DESIGN STRUCTURE FOR DOUBLE-WIDTH INSTRUCTION QUEUE FOR INSTRUCTION EXECUTION
摘要 A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally comprises a processor, which generally comprises a cache, a dual instruction queue comprising a first queue and a second queue, an execution unit, and circuitry. The circuitry is configured to receive branch instructions, issue instructions for the branch instruction's first path to the first queue, issue instructions for the branch instruction's second path to the second queue, and determine if the branch instruction follows the first or second path. The control circuitry is further configured to, upon determining that the branch instruction follows the first path, provide the instructions for the first path from the first queue to the execution unit, and upon determining that the branch instruction follows the second path, provide the instructions for the second path from the second queue to the execution unit.
申请公布号 US2008162905(A1) 申请公布日期 2008.07.03
申请号 US20080048387 申请日期 2008.03.14
申请人 发明人 LUICK DAVID A.
分类号 G06F9/30 主分类号 G06F9/30
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