发明名称 REDUCING IDLE LEAKAGE POWER IN AN IC
摘要 <p>A method to reduce idle leakage power in I/O pins of an integrated circuit using external circuitry. Initially, I/O pins on a package are subdivided into those that will also remain powered up and those that will power down during idle state. When a system enters a low power mode, a signal is sent to the external circuitry. The signal notifies the I/O pins that always remain powered up to notify the external circuitry to power down the other set of I/O pins.</p>
申请公布号 WO2008079518(A1) 申请公布日期 2008.07.03
申请号 WO2007US83036 申请日期 2007.10.30
申请人 INTEL CORPORATION;HACKING, LANCE;KUTTANNA, BELLIAPPA;PATEL, RAJESH;CHOUBAL, ASHISH;FLETCHER, TERRY;VARNUM, STEVEN;PATEL, BINTA 发明人 HACKING, LANCE;KUTTANNA, BELLIAPPA;PATEL, RAJESH;CHOUBAL, ASHISH;FLETCHER, TERRY;VARNUM, STEVEN;PATEL, BINTA
分类号 G06F1/28 主分类号 G06F1/28
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