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发明名称
半导体装置
摘要
当行间隔件设于与TFT重叠的区时,有将在相互附接一对基板时施加压力之利害关系,其可能导致对TFT的不利影响及裂缝形成。在行间隔件下方以无机材料形成之虚拟层,该行间隔件形成于与TFT重叠之位置。虚拟层位于与TFT重叠之位置,使得于附接该对基板的步骤中施加至TFT之压力被分布及释放。较佳地以如像素电极的相同材料形成之虚拟层,以形成该虚拟层而不会增加处理步骤的数量。
申请公布号
TW200827893
申请公布日期
2008.07.01
申请号
TW096136340
申请日期
2007.09.28
申请人
半导体能源研究所股份有限公司
发明人
藤川最史;细谷邦雄
分类号
G02F1/136(2006.01)
主分类号
G02F1/136(2006.01)
代理机构
代理人
林志刚
主权项
地址
日本
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