| 摘要 |
A first AD converter subjects an analog signal to AD conversion by a first AD clock, and a second AD converter subjects the same analog signal to AD conversion by a second AD clock that is shifted in phase from the first AD clock by half cycle. FF circuits store the AD conversion results of the first AD converter and the second AD converter by the first AD clock and the second AD clock, respectively. FF circuits store the data of the FF circuits by the first AD clock, separately. A DPRAM writes the respective data that are stored by the FF circuits by the first AD clock as a group of data, divides the group of written data into the respective data, and reads the respective data by a logic clock in twice to output the data to an integration circuit. |
