USING COMMON MODE DIFFERENTIAL DATA SIGNALS OF DDR2 SDRAM FOR CONTROL SIGNAL TRANSMISSION

摘要

A double-data-rate two synchronous dynamic random access (DDR 2 ) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having a common output wherein a high-speed output path and a low-speed output path are coupled together by an output coupling and further coupled to the common output of the memory core.