摘要 |
A redundant memory array (300) has r columns of redundant memory cells (306), r redundant senses (312), and a redundant column decoder (308). Redundant address registers (332) store addresses of defective regular memory cells. Redundant latches (338) are provided in n groups of r latches. Redundancy comparison logic (330) compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal (333) to disable the regular senses (310) for one of the n groups of m columns, an ENABLE_LATCH signal (334) to one of the n groups of m columns to disable corresponding regular senses, and one of r REDO signals (336) to a respective one of the r redundant latches (338) in one of the n groups that is disabled. The selected one of the redundant latches (338) activates one of the r redundant senses (312) to access a redundant column. |
申请人 |
ATMEL CORPORATION;BARTOLI, SIMONE;SURICO, STEFANO;SACCO, ANDREA;MOSTOLA, MARIA |
发明人 |
BARTOLI, SIMONE;SURICO, STEFANO;SACCO, ANDREA;MOSTOLA, MARIA |