发明名称 IC PACKAGE ENCAPSULATING A CHIP UNDER ASYMMETRIC SINGLE-SIDE LEADS
摘要 A multi-chip IC package encapsulates a chip under asymmetric longer single-side leads. The package mainly comprises a plurality of leads that have asymmetric length at two sides of a leadframe, a plurality of die-attach tape strips, a first chip having a plurality of single-side pads under the longer side leads, at least a second chip disposed above the longer side leads, a plurality of bonding wires and a molding compound. The die-attach tape strips are mutually parallel and adhered onto the lower surfaces of the longer side leads to adhere the first chip. There is at least a mold-flow channel formed through the first chip, the longer side leads and the die-attach tape strips. The bonding wires electrically connect the single-side pads of the first chip to the leads at the two sides of the leadframe through a non-central gap. The molding compound encapsulates the first chip, the second chip, the bonding wires and portions of the leads at the two sides of the leadframe and fills up the mold-flow channel. The mold-flow channel formed by means of the die-attach tape strips may increase the encapsulated area of the first chip by the molding compound to enhance product reliability of semiconductor package.
申请公布号 US2008150100(A1) 申请公布日期 2008.06.26
申请号 US20060643860 申请日期 2006.12.22
申请人 POWERTECH TECHNOLOGY INC. 发明人 HUNG CHIA-YU;LEU CHAO-HSIANG;CHIU TSENG-SHIN
分类号 H01L23/495 主分类号 H01L23/495
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