发明名称 Decomposing architectural operation into speculative and architectural micro-operations for speculative execution of others and for violation check
摘要 Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may be many clock cycles away from the issue engine. The issue engine categorizes operations as at least one of either a speculative operations which perform computations, or an architectural operations which has potential to fault or cause an exception. Potentially excepting operations may be decomposed into two separate micro-operations: a speculative micro-operation, which is used to generate data results speculatively so that operations dependent on the results may be speculatively issued, and an architectural micro-operation, which signals the faulting condition for the excepting operation. A STORE operation becomes an architectural operation and all previous faulting conditions may be guaranteed to have evaluated before a STORE is issued.
申请公布号 US7392369(B2) 申请公布日期 2008.06.24
申请号 US20060406879 申请日期 2006.04.18
申请人 INTEL CORPORATION 发明人 BAXTER JEFFERY J.;HAMMOND GARY N.;ZAIDI NAZAR A.
分类号 G06F9/312;G06F9/00;G06F9/318;G06F9/38 主分类号 G06F9/312
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