| 摘要 |
Data signals received in an integrated circuit are coupled to a receiver and to an on-chip data acquisition system which takes measurement samples of the data signal in response to a measurement request. The measurement request is synchronized with an asynchronous sample clock signal generating a capture signal and a counter reset signal. A counter measures the number of sample clock cycles between measurement requests. On receipt of a measurement request, the capture signal triggers the storage, as capture data, the preset number of cycles in the counter and the measurement samples in a register. The counter is synchronously reset and the capture data is sent to off-chip storage. The off-chip storage stores an arbitrary amount of capture data and the area on-chip is greatly reduced for the on-chip data acquisition. An off-chip analysis is used to construct an effective time base for the capture data for signal analysis
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