| 摘要 |
An architecture for a semiconductor static random access memory (SRAM) is described. In one example, a first set or group or stage of SRAM banks are coupled to a first data bus formed using bit line pairs, and a second set or group or stage of SRAM banks are coupled to a second data bus formed using other bit line pairs. The number of banks coupled to each bit line pair is determined by the SRAM's operating frequency and size. Each data bus is coupled to a sense amplifier. The output from the sense amplifier is then coupled to the bit line pair of a group of SRAM banks. This adjacent group has staging logic coupled to each SRAM bank to store the output of the SRAM bank until the contents from the first group is placed on the bit line of the adjacent stage of SRAM banks. The output from either the first stage or from one of the SRAM banks in the adjacent stage's SRAM banks, which had been stored in the adjacent stage's staging logic, is driven to the sense amplifier coupled to the adjacent stage. Successive stages of SRAM banks can be coupled together until an arbitrary number of stages of SRAM banks have been coupled together.
|
