| 摘要 |
Embodiments of a clock repeater and phase-error correcting circuit are generally described herein. Other embodiments may be described and claimed. In some embodiments, a clock repeater and phase-error correcting circuit may include a polyphase network having a non-symmetrical frequency response selected to reduce static phase error from a multi-phase clock signal, and an output buffer to buffer and to amplify the phase-corrected multi-phase clock signal.
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