NON-VOLATILE MEMORY EMBEDDED IN A CONVENTIONAL LOGIC PROCESS AND METHODS FOR OPERATING SAME

摘要

A non-volatile memory system (301) including an array of cells (100), each having an access transistor (110) and a capacitor (120) sharing a floating gate (116) The access transistors (110) in each row are fabricated in separate well regions (NWO), which are independently biased Within each row, the source of each access transistor (111) is coupled to a corresponding virtual ground line (VG), and each capacitor structure (120) is coupled to a corresponding word line (122) Alternately, the source of each access transistor (111) in a column is coupled to a corresponding virtual ground line (VG) Within each column, the drain of each access transistor (112) is coupled to a corresponding bit line (BL) Select memory cells in each row are programmed by band-to-band tunneling Bit line biasing prevents programming of non-selected cells of the row Programming is prevented in non-selected rows by controlling the well region voltages of these rows Sector erase operations are implemented by Fowler-Nordheim tunneling.