| 摘要 |
The present invention provides an integrated circuit for providing ESD protection. The integrated circuit comprises a transistor device having at least one interleaved finger having a substrate region, a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further comprises at least one highly doped junction formed adjacent to the source region to measure voltage potential of the substrate region. The integrated circuit further comprises a switching circuit coupled to the at least one highly doped junction such that the voltage potential is transferred to the switching circuit to either draw the full ESD current or trigger to draw the full ESD current.
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