发明名称 DIGITALLY FILTERED PULSE WIDTH MODULATION
摘要 PROBLEM TO BE SOLVED: To solve the problem that a continuous time output stage of a DAC (digital to analog converter) requires a method of minimizing inter-symbol interference and improving effects of clock characteristics. SOLUTION: The digital to analog converter (Fig 1A) includes a noise shaping modulator (102) for modulating an input digital data stream (101), a plurality of output elements (103) for generating a plurality of intermediate data streams from a modulated output stream from the modulator, and an output summer (106) for summing the intermediate data streams to generate an output analog stream. The noise shaping modulator balances an edge transition rate of the output elements so that the edge transition rate of two selected elements is approximately equal. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008136202(A) 申请公布日期 2008.06.12
申请号 JP20070284558 申请日期 2007.10.31
申请人 CIRRUS LOGIC INC 发明人 MELANSON JOHN LAURENCE
分类号 H03M7/32;H03H17/02;H03H17/06;H03M3/00 主分类号 H03M7/32
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