METHOD FOR REDUCING CHARGE LOSS IN ANALOG FLOATING GATE CELL
摘要
<p>A voltage reference circuit provides a reference voltage in response to a programmed threshold voltage of a first non-volatile memory (NVM) transistor. The threshold voltage of the first NVM transistor is programmed by applying a programming voltage to commonly connected source/drain regions of a tunneling capacitor, which shares a floating gate with the first NVM transistor. During normal operation of the voltage reference circuit, the source/drain regions of the tunneling capacitor are connected to a second NVM transistor that has the same electrical and thermal characteristics as the floating gate of the first NVM transistor. As a result, charge loss from the floating gate of the first NVM transistor is advantageously minimized.</p>
申请公布号
WO2008070578(A2)
申请公布日期
2008.06.12
申请号
WO2007US86175
申请日期
2007.11.30
申请人
CATALYST SEMICONDUCTOR, INC.;SPOREA, RADU A.;GEORGESCU, SORIN S.;POENARU, ILIE MARIAN I.
发明人
SPOREA, RADU A.;GEORGESCU, SORIN S.;POENARU, ILIE MARIAN I.