发明名称 GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME, AND METHOD FOR FABRICATING MEMORY AND CMOS TRANSISTOR LAYOUT
摘要 A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive layer. A liner conductive layer is formed to cover the dielectric layer and the pad conductive layer. A portion of the liner conductive layer and a portion of the pad conductive layer are removed to expose a surface of the pad oxide layer to form a conductive spacer. The pad oxide layer is removed and a gate oxide layer is formed over the substrate. A first gate conductive layer and a second gate conductive layer are sequentially formed over the gate oxide layer. A portion of the gate oxide layer is removed and a cap layer to fill the opening.
申请公布号 US2008135943(A1) 申请公布日期 2008.06.12
申请号 US20070670429 申请日期 2007.02.02
申请人 PROMOS TECHNOLOGIES INC. 发明人 CHIEN JUNG-WU
分类号 H01L27/092;H01L29/78 主分类号 H01L27/092
代理机构 代理人
主权项
地址