| 摘要 |
A semiconductor memory device includes a sense amplifier SA, a pair of bit lines BLT, BLB, a transfer switch SW provided between the sense amplifier SA and the pair of bit lines BLT, BLB, a precharge circuit PC that precharges the sense amplifier SA and the pair of bit lines BLT, BLB at the same potential, and a control circuit CTL. The control circuit CTL sets the transfer switch SW in the off state in the state before data is written or read, and turns on the transfer switch SW when writing or reading data via the pair of bit lines BLT, BLB. With this arrangement, a defective current flowing to the sense amplifier SA can be decreased, even when a word line WL and a bit line BL are shortcircuited.
|
