| 摘要 |
<p>A wafer level stack chip package includes uppermost semiconductor chip (62) including inner connection terminals (57a, 57b, 57c) which are flip-chip bonded to through holes (59a, 59b, 59c) filled with conductive filling material of a lower semiconductor chip(s) (61). A wafer level stack chip package formed by three-dimensionally stacking semiconductor chip, comprises (i) a redistribution substrate comprising sequential first dielectric layer (45) in a predetermined pattern, redistribution layer (47) in a predetermined pattern, second dielectric layer (48), and substrate pads (49) exposed from the second dielectric layer and connected to the redistribution layer; a lower semiconductor chip(s) and uppermost semiconductor chip comprising sequential semiconductor substrate , passivation layer, chip pads, redistribution layer electrically connected to the chip pads, polymeric layer having holes for partially exposing the redistribution layer, inner connection terminals, and conductive filling material for filling the through holes; (ii) a filling layer for filling areas between two chips among the lower semiconductor chips and the uppermost semiconductor chip to be stacked on the redistribution substrate, thus protecting the inner connection terminals; (iii) a metal lid for coating the surfaces of the lower semiconductor chips, the uppermost semiconductor chip, and the redistribution substrate except for the first dielectric layer of the redistribution substrate; and (iv) external connection terminals (90) formed on and electrically connected to the exposed redistribution layer from the first dielectric layer of the redistribution substrate. The inner connection terminals of the uppermost semiconductor chip are flip-chip bonded to the through holes filled with the conductive filling material of the lower semiconductor chip. An independent claim is also included for a method for manufacturing a wafer level stack chip package.</p> |
