发明名称 Synchronization circuit for DDR IO interface
摘要 An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a first strobe signal having an unknown phase in relation to a local clock signal when receiving data from a memory. The second circuit may be configured to synchronize the first strobe signal with the local clock signal by (i) generating one or more second strobe signals and (ii) inserting a predetermined cycle delay between the one or more second strobe signals and the local clock signal.
申请公布号 US7385861(B1) 申请公布日期 2008.06.10
申请号 US20060465514 申请日期 2006.08.18
申请人 AMBARELLA, INC. 发明人 ZHU XIAOJUN
分类号 G11C7/00 主分类号 G11C7/00
代理机构 代理人
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