发明名称 |
Stress liner for integrated circuits |
摘要 |
In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.
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申请公布号 |
US7384833(B2) |
申请公布日期 |
2008.06.10 |
申请号 |
US20060350160 |
申请日期 |
2006.02.07 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
POLISHCHUK IGOR;RAMKUMAR KRISHNASWAMY;LEVY SAGY CHAREL |
分类号 |
H01L21/336;H01L21/8234 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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