发明名称 LOOK-UP TABLE CASCADE CIRCUIT, LOOK-UP TABLE CASCADE ARRAY CIRCUIT, AND CONTROL METHOD OF PIPELINE THEREOF
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a look-up table cascade circuit in which a plurality of LUTs constituted in a general-purpose memory circuit are cascaded with flexible input/output structure with simple constitution and control. <P>SOLUTION: N LUTs (look-up tables), which realize a desired logical function, are cascaded. An LUT circuit unit of each stage is composed of an LUT 10 comprising a memory cell array; an input selection circuit (a main low decoder 11, a subdecoder 12 and a column decoder 13) which selects each memory cell to be read by the LUT 10 based on an input variable; an output circuit (an output switch circuit 15 and an output latch circuit 16) which outputs data selected by the input selection circuit as an output variable Y by selectively connecting input/output routes; and a connection circuit (a selector circuit 14) which inputs an external input variable EI and the output variable Y of prestage and selectively distributes and outputs an external output variable EO and an input variable of poststage wholly or partially in accordance with preliminarily fixed connection information. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2008129824(A) 申请公布日期 2008.06.05
申请号 JP20060313637 申请日期 2006.11.20
申请人 ELPIDA MEMORY INC 发明人 KAJITANI KAZUHIKO
分类号 G06F5/00 主分类号 G06F5/00
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