| 摘要 |
PROBLEM TO BE SOLVED: To provide a technology by which interrupt processing of a CPU is executed at an early stage. SOLUTION: A CPU is included in bus masters 1-4. Each of the bus masters 1-4 accesses bus slaves 5, 6 using a common bus BUSS. A bus access arbitration circuit 7 arbitrates access requests to the bus BUSS in the bus masters 1-4. When an interrupt request is notified, an interrupt controller 8 notifies the CPU of execution of the interrupt processing and outputs a priority processing request signal PPR for requesting priority acceptance of the access request of the CPU to the bus access arbitration circuit 7. When the priority processing request signal PPR is input, the bus access arbitration circuit 7 preferentially accepts the access request of the CPU to other bus masters 2-4. COPYRIGHT: (C)2008,JPO&INPIT
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