| 摘要 |
A semiconductor device designing method of the present invention corresponds to a method for designing a clock synthesization type semiconductor device, which is comprised of: a rough CTS (clock tree synthesis) step for performing the CTS within an adjustable range in multiple phases; a timing check step for judging whether or not transmission/reception of data are carried out under normal condition based upon a propagation time of data and an arrival time of a clock signal between flip-flops; a detailed timing analyzing step for judging whether or not the transmission/reception of the data can be carried out under the normal condition by switching a phase of a clock signal, or by increasing/decreasing a buffer in a half way of the clock tree as to supply timing of the clock signal; and a re-allocating step of a CLK net, for allocating a phase of such a clock signal which does not cause a timing violation every flip-flop based upon the result of the detailed timing analyzing step.
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