发明名称 |
Circuit to Reduce Power Supply Fluctuations in High Frequency/High Power Circuits |
摘要 |
The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to the output of the first divider, thereby lessening current surges.
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申请公布号 |
US2008133957(A1) |
申请公布日期 |
2008.06.05 |
申请号 |
US20080014830 |
申请日期 |
2008.01.16 |
申请人 |
BOERSTLER DAVID WILLIAM;HAILU ESKINDER;RILEY MACK WAYNE;WANG MICHAEL FAN |
发明人 |
BOERSTLER DAVID WILLIAM;HAILU ESKINDER;RILEY MACK WAYNE;WANG MICHAEL FAN |
分类号 |
G06F1/10 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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