| 摘要 |
A simulation model for a system wherein data passes from a source domain to a destination domain, such source and destination domains operating with different, asynchronous clocks provided to the source and destination domains. The model includes a three-stage delay network fed by data from the source domain in response to clock provided to operate the source domain. The network operates in response to clocks provided to operate the destination domain. The model includes a selector having inputs fed by outputs of the three delays and an output fed to the destination domain, such selector randomly providing to the output of such selector outputs of the each of the delays from the three stage delay network. The selector output is randomly chosen only when the data in the source domain changes logical state from a logic low to high or from a logic high to low. Otherwise, if this were performed on every clock of the destination domain, the randomness would not be evenly distributed between all three-delay stages.
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