Computer architecture containing processor and decoupled coprocessor

摘要

A computer system comprises a first processor 1 and a second processor 2 for use as a coprocessor to the first processor 1 . The system has a main memory 3 . The system also has a decoupling element 8 such that instructions are passed to the second processor 2 from the first processor 1 through the decoupling element 8 . This has the effects that the second processor 2 consumes instructions derived from the first processor 1 through the decoupling element 8 , and that the second processor 2 receives data from and writes data to the memory 3 . The processing of instructions by the second processor 2 can thus be decoupled from the operation of the first processor 1. This is particularly effective for processing of a computationally intensive task (such as a media computation) on an architecture with a general purpose first processor 1 , using a second processor 2 adapted for the computationally intensive task. This can effectively be combined with use of a buffer memory 5 adapted to exchange data particularly rapidly with the memory 3 in response to memory instructions, together with a further decoupling element 6 to decouple the buffer memory 5 from the first processor 1.