| 摘要 |
The present invention provides a logic synthesis method and the like that can shorten the execution time and the confirmation time required for logic re-synthesis and logic equivalence checking. The logic synthesis method characteristically includes the steps of: extracting logically different portions between an existing gate level logic circuit and a modified Hardware Description Language (HDL) description; hierarchizing the different portions between the existing gate level logic circuit and the modified HDL description; generating a gate level logic circuit by logically combining the hierarchized portions of the modified HDL description; and replacing the hierarchized portions of the existing gate level logic circuit with the gate level logic circuit. By this method, a layer containing detected different portions is automatically generated in logic equivalence checking between a modified HDL and a gate level logic circuit, so that logic synthesis can be performed in a unit smaller than the unit for the conventional logic synthesis. Thus, the execution time and the confirmation time required for logic re-synthesis and logic equivalence rechecking can be shortened.
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