发明名称 SPACERS BETWEEN BITLINES IN VIRTUAL GROUND MEMORY ARRAY
摘要 According to one exemplary embodiment, a method of fabricating a virtual ground memory array, which includes bitlines situated in a substrate, includes forming at least one recess in the substrate between two adjacent bitlines, where the at least one recess is situated in a bitline contact region of the virtual ground memory array, and where the at least one recess defines sidewalls and a bottom surface in the substrate. The step of forming the at least one recess includes using hard mask segments as a mask, where each of the hard mask segments is situated over a bitline. The method further includes forming a spacer in the at least one recess, where the spacer reduces bitline-to-bitline leakage between the adjacent bitlines. The method further includes forming stacked gate structures before forming the at least one recess, where each stacked gate structure is situated over and perpendicular to the bitlines.
申请公布号 EP1925029(A1) 申请公布日期 2008.05.28
申请号 EP20060802940 申请日期 2006.09.06
申请人 SPANSION LLC 发明人 OGAWA, HIROYUKI
分类号 H01L27/115;H01L21/8247 主分类号 H01L27/115
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