| 摘要 |
An erasing circuit of a non-volatile semiconductor memory device is provided to suppress chip area without complicated control of erase processing and not forming a boundary region to insulate each memory cell block electrically. A row decoder(41,42) switches a voltage applied to a word line of a memory cell block in the unit of memory cell block. A voltage supply source is installed in every memory cell array block of a memory cell block group, and supplies a reference voltage or a positive voltage for erasing to the row decoder of the memory cell block of one memory cell block group. Each voltage supply source outputs the reference voltage when an erase target block is included in one memory cell block supplying a voltage between the memory cell block groups, and outputs the positive voltage for erasing when the erase target block is not included.
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