| 摘要 |
PROBLEM TO BE SOLVED: To provide an image reader capable of speeding up read. SOLUTION: The outputs of AFEs 42, 43 are changed in the period of fourth and eighth clocks. When a third clock is completed, the chip selection of the AFE 42 is changed from a low level to a high level and the output of the AFE 42 is set to be in high impedance. The chip selection of the AFE 43 is changed from a high level to a low level, upper 8 bits of a fourth channel are outputted in the high level period of a fifth clock, and lower 8 bits are outputted in a low period. Similarly, fifth and sixth channels are outputted in sixth and seventh clock periods, respectively, and the AFE 43 is changed to the AFE 42 again in an eighth clock. A time period during the change is performed lasts 40 ns and is set to time shorter than a period of 60 ns when a digital signal is outputted form the AFEs 42, 43. COPYRIGHT: (C)2008,JPO&INPIT
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