INTEGRATED CIRCUIT AND METHOD FOR BUFFERING TO OPTIMIZE BURST LENGTH IN NETWORKS ON CHIPS,申请号EP20050739743-传众专利搜索

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发明名称	INTEGRATED CIRCUIT AND METHOD FOR BUFFERING TO OPTIMIZE BURST LENGTH IN NETWORKS ON CHIPS
摘要
申请公布号	EP1751667(B1)	申请公布日期	2008.05.21
申请号	EP20050739743	申请日期	2005.05.13
申请人	KONINKLIJKE PHILIPS ELECTRONICS N.V.	发明人	RADULESCU, ANDREI;GOOSSENS, KEES, G., W.
分类号	G06F13/42	主分类号	G06F13/42
代理机构		代理人
主权项
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