| 摘要 |
A memory includes an input pad for receiving an input signal and a first circuit. The first circuit is configured to receive a first signal in response to the input signal and receive a second signal and provide a third signal in response to at least one of the first signal and the second signal indicating a request to enter a deep power down mode. The memory includes a second circuit configured to provide a fourth signal indicating an entry to the deep power down mode in response to the third signal.
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