| 摘要 |
A programmable logic device test generation tool is provided that produces test configuration data and test vectors for testing programmable logic device integrated circuits. A graph generation tool converts a netlist or other circuit description of a programmable logic device integrated circuit into a graph having nodes and edges. A timing analysis tool may be used to help produce test constraints. Based on the test constraints, an automatic test generator processes the graph to produce the test configuration data and test vectors. In processing the graph with the automatic test generator, the graph may be divided into multiple testable subgraphs. Each subgraph may be processed using an iterative approach in which a cost function threshold is adjusted in a number of steps until a target test coverage is obtained or processing saturates.
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