发明名称 |
Integrated packet bit error rate tester for 10G SERDES |
摘要 |
An integrated packet bit error rate tester includes a packet transmit circuit that has a first memory for storing transmit packet data and is connectable to a channel under test. A packet receive circuit includes a second memory for storing received packet data and is connectable to the channel under test. An interface is used for programming the packet transmit and packet receive circuits. The packet transmit circuit can generate an arbitrary 10G SERDES packet in response to commands from the interface. The packet receive circuit can determine a bit error rate of the channel under test. The second memory can capture received packet data upon any one of (a) after a pre-programmed pattern is detected, (b) after a pre-programmed pattern is lost, and (c) after an error is detected.
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申请公布号 |
US7373561(B2) |
申请公布日期 |
2008.05.13 |
申请号 |
US20030681244 |
申请日期 |
2003.10.09 |
申请人 |
BROADCOM CORPORATION |
发明人 |
BAUMER HOWARD A;WANG PEIQING |
分类号 |
G06F11/263;G01R31/08;G01R31/28;G06F3/00;G06F11/16;G21C17/00;H04J1/16;H04J3/04;H04J3/14;H04L;H04L1/00;H04L12/26;H04L12/40;H04Q11/00 |
主分类号 |
G06F11/263 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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